Job bank for everyone

 

Design Engineer

Closing Date 2016-11-25

TalentSource is an Executive Search company providing value-added talent solution to MNC and local clients. We build meaningful and rewarding relationships between top-tier executives and our valued clients, while actively catering to both parties� need for confidentiality, dignity, integrity and professionalism.

Responsibilities

  • Develop and implement plans to synthesize and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.

  • Design complex clock structure to meet tight skew requirements

  • Simulate and analyse log and report generated from EDA tools and make design trade-off to get the required results within the scheduled milestones.

  • Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.

  • Ensure the implemented design meets the new double patterning rules required for process node below 20nm as well as design rule for manufacturing.

  • Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.

Requirements

  • Bachelor/ Master Degree in Electronic Engineering with 2-5 years relevant experience

  • Experience of logic synthesis, test insertion, PnR and backend checks

  • Excellent verbal and written communication skills. Strong interpersonal skills

  • Knowledge of FPGA is an advantage

To apply this position, please send resume in WORD format to search@talentsourceconsulting.com


Job ID642
IndustrySemiconductor / Wafer Fabrication
SpecializationEngineering - Electronic/Communication
LevelSenior Executive
Job TypePermanent
LocationSingapore
CountrySingapore
SalaryNegotiable